using remote rom with the 660 bridge application note an-ppc-012 dale elson april, 1996 the IBM27-82660 powerpc to pci bridge and memory controller allows the boot rom to be located on an isa or other tertiary bus. mpra12apu-01
2 an-ppc-012 using remote rom with the 660 bridge dale elson the IBM27-82660 powerpc to pci bridge and memory controller allows the boot rom to be located on an isa or other tertiary bus. this application note describes the remote rom mode of the IBM27-82660 powerpc to pci bridge and memory controller (660). remote rom mode was documented in initial versions (mpr660umu-01 and earlier) of the 660 user's manual. the remote rom mode documentation was removed from the most recent (mpr660umu-02) version of the user's manual because the function was not supported at the time that the user's manual was released. the remote rom mode is now supported and will continue to be supported. this application note serves as an addendum to mpr660umu-02. the information in this application note will be included in subsequent revisions of the 660 user's manual. 1 pin descriptions information about remote rom mode operation is added to three of the signal descriptions in section 2 of the 660 user's manual. these additions are indicated in bold in table 1. table 1. 660 bridge signal descriptions signal 663 664 description rom_oe# e o 47 rom output enable. rom_oe# enables direct-attached rom. the signal is always high for remote rom. rom_we# e o 60 rom write enable. write enable for flash rom for direct-attach rom. the signal is always high for remote rom. aos_rr_mmrs i 166 o 69 all ones select/rom remote/mask mem_rd_smpl. this signal is used to force the data bus to 64 one-bits when the cpu reads memory of pci space that is unoccupied. to force all ones, this signal must be asserted on the cpu_clk that the cpu read latch samples data. when rom_load is asserted, this signal is used to determine the location of the rom. when rom_remote is deasserted, it indicates that the rom is locally on the pci bus. in this case, rom data always arrives on pci_ad[31:24]. when rom_remote is asserted, the rom is assumed to be on a tertiary bus (such as the isa bus). in this case, rom data arrives like all other one-byte pci targetsefirst byte on pci_ad[7:0], second byte on pci_ad[15:8], etc. when the pci is burst reading memory, mask_mem_rd_smpl is asserted after the first mem_rd_smpl. it then stays asserted until the pcitomem read latch is empty. note: on pci burst reads of memory, the pcitomem read latch keeps getting refilled as long as data from the memory is available before the pci uses it up.
3 an-ppc-012 2 rom operations the following sections are added to section 7 of the 660 user's manual. the first rom access method (remote rom mode) attaches the rom device to an external pci agent which supports the powerpc reference platform rom space map and access protocol. cpu bus master transfers to rom space are forwarded to the pci bus and claimed by the pci agent, which supplies the rom device data. this pci device is typically a pci to isa bridge. the rom device attaches to the isa bridge through the isa bus lines, thereby saving a pci bus load. the 660 supplies write-protect capability in this mode. the rom mode is indicated to the 660 on the strapping pin configuration bits during power-on-reset (por). 2.1 remote rom mode in a system that uses the remote rom mode, the rom device attaches to a pci agent. when a cpu bus master reads from memory addresses mapped to rom space, the 660 arbitrates for the pci bus and then masters a memory read transaction on the pci bus. the pci agent claims the transaction and supplies the rom device data. cpu writes to the rom and rom write-protection operations are also forwarded to the pci agent. as shown in figure 1, the rom access flows from the cpu to the 660 over the cpu bus, from the 660 to the pci agent over the pci bus, and from the pci agent to the rom device. the rom device attaches to the pci agent, not to the pci_ad lines, so a pci bus load is saved by the remote rom method. figure 1. remote rom connections rom address data control system 660 bridge 60x cpu 60x bus pci bus pci agent 2.1.1 remote rom reads for remote rom reads, the 660 arbitrates for the pci bus, initiates eight single-byte pci accesses, releases the pci bus, and completes the cpu transfer. the eight single bytes of rom data are assembled into a double-word in the 663 and passed to the cpu. figure 2 shows the beginning of the operation, including the first two pci transac- tions. figure 3 shows the last part of the operation, including the last two pci transactions. during and following reset, compliant pci agents are logically disconnected from the pci bus except for the ability to respond to configuration transactions. these agents have not yet been configured with necessary operational parameters. pci agents capable of the remote rom access protocol reset with the ability to respond to remote rom accesses before being fully configured. the cpu begins reading instructions at fff0 0100h before it can configure the pci devices. the rom read discussion assumes that the system is in big-endian mode. for the effects of little-endian mode operation on rom reads, see section 2.1.1.4.
4 an-ppc-012 figure 2. remote rom read initial transactions n pci_clks (1) n pci_clks (4) n pci_clks (4) s add a cmd byte enables data a stop# not asserted during the transaction. (1) this delay is controlled by the system arbiter. s (4) this delay is paced by the remote rom controller. s (2) a add b data b b b b a a a b b a s b a a (3) (3) (3) irdy# is always asserted as shown. irdy# is deasserted on the clock that trdy# is sampled active. cpu_clk cpu_addr ts# aack# ta# cpu_data pci_clk pci_req# pci_gnt# pci_ad [664] pci_ad [pci] c/be[3:0]# [664] devsel# frame# irdy# trdy# the pci agent may assert trdy# as soon as it samples frame# active. assumes that pci bus now stays parked on 660/cpu. (2) pci bus not parked on 660/cpu. if the pci bus is parked on the cpu, then frame# will be asserted here. 2.1.1.1 remote rom read sequence in response to a cpu bus read in the 4g 2m to 4g address range, the 660 requests the pci bus from the pci arbiter. when the pci bus is granted (or if the bus is already parked on the cpu), the 660 initiates a series of pci memory-read transactions as shown in table 2 for a cpu read from ffe0 0000h to ffff ffff. note that the last column in table 2 shows the effect of little-endian mode operation. see section 2.1.1.4. the address of the first transaction is the low-order byte of the double-word pointed to by the cpu address (see section 2.1.1.2). the 660 expects the low-order byte of rom data in the 8-byte double-word to be returned on pci byte lane 0, pci_ad[7:0]. as shown in the 660 then masters seven more pci read transactions, each time receiving
5 an-ppc-012 back one byte of rom data and driving it onto the cpu data bus as shown in table 2. note that the byte enables are incrementing within each 4-byte word pointed to by the pci address. at the completion of the eighth pci read, the 660 drives the assembled double-word onto the cpu data bus. the 660 then signals completion of the transfer to the cpu. figure 3. remote rom read final transactions n pci_clks (3) n pci_clks (3) s add g cmd byte enables data g stop# not asserted during the transaction. (1) assumes pci bus parked on 660/cpu. (3) this delay is controlled by the remote rom controller. the pci agent may assert trdy# as soon as it samples frame# active. add h data h h h h g g g h h g s h g g (1) (1) s (2) irdy# is always asserted as shown. irdy# is deasserted on the clock that trdy# is sampled active. cpu_clk cpu_addr ts# aack# ta# cpu_data pci_clk pci_req# pci_gnt# pci_ad [664] pci_ad [pci] c/be[3:0]# [664] devsel# frame# irdy# trdy# remote rom reads are not pipelined. the 660 does not assert aack# to the cpu until the end of the remote rom read sequence. the 660 asserts pci_req# throughout the entire remote rom read sequence.
6 an-ppc-012 table 2. remote rom read sequence, cpu address = fffx xxx0 pci access # pci bus read memory address pci_ad[31:0] byte enables pci_c/be[3:0]# rom addr rom data big endian cpu_data [0:63] little endian cpu_data [0:63] 1 fffx xxx0h 1110 0 a e e 2 fffx xxx0h 1101 1 b e e 3 fffx xxx0h 1011 2 c e e 4 fffx xxx0h 0111 3 d e e 5 fffx xxx4h 1110 4 e e e 6 fffx xxx4h 1101 5 f e e 7 fffx xxx4h 1011 6 g e e 8 fffx xxx4h 0111 7 h abcd efgh hgfe dcba 2.1.1.2 address, transfer size, and alignment the initial pci address generated during the remote rom read sequence is formed by copying the high-order 29 bits of the cpu address, and forcing the three low order bits pci_ad[2:0] to 000b. this generates a base address that is aligned on an 8-byte boundary. while reading the lower 4 bytes, the 660 indicates which byte it is requesting using the pci byte enables c/be[3:0]#. after the first four bytes of rom data are read, the 660 increments the address on the pci_ad lines by 4 before executing the second four pci reads. the cpu read address need not be aligned on an 8-byte boundary. a cpu read from any address (in rom space) of any length that does not cross an 8byte boundary within a double-word returns all eight bytes of that double-word data from the rom. for example, the operations shown in table 2 could have been caused by a cpu memory read to fff0 0100h, fff0 0101h, or fff0 0105h. errors occurring during remote rom reads are handled as usual for the error type. no special rules are in effect. 2.1.1.3 burst reads the 660 supports burst reads in remote rom mode. the 660 supports a pseudo burst mode, which supplies the same eight bytes of data (from the rom) to the cpu on each beat of a 4-beat cpu burst. a burst rom read begins with the 660 executing a single-beat rom read operation, which assembles eight bytes of rom data into a double-word on the cpu data bus. for a burst rom read, the 660 asserts ta# for four cpu_clk cycles, with aack# asserted on the fourth cycle. the same data remains asserted on the cpu data bus for all four of the data cycles. for a single-beat read, the 660 asserts ta# and aack# for one cpu_clk cycle, and the cpu completes the transfer. 2.1.1.4 endian mode considerations in little-endian mode, the address munging done by the cpu has no effect because pci_ad[2:0] are forced to 000 during the address phase by the 660 at the beginning of the transaction. however, in little-endian mode the byte swapper is enabled, so the
7 an-ppc-012 bytes of rom data returned to the cpu are swapped as shown in the last column of table 2. 2.1.1.5 4-byte reads the 660 handles 4-byte rom reads (and all rom reads of less than 8 bytes) as if they were 8-byte reads. all 8 bytes are gathered by the 660, and all 8 bytes are driven onto the cpu data bus.
8 an-ppc-012 2.1.2 remote rom writes while the 660 is configured for remote rom operation, the 660 forwards all cpu to rom write transfers to the pci bus as memory writes. the pci agent that is controlling the remote rom acts as the pci target during cpu to rom write transfers, executes the write cycle to the rom, and may provide rom write-protection. figure 4. remote rom write n pci_clks (1) n pci_clks (4) add cmd byte enables data stop# not asserted during the transaction. (1) this delay is controlled by the system arbiter. s s (4) this delay is paced by the remote rom controller. the pci agent may assert trdy# as soon as it samples frame# active. (2) (2) pci bus not parked on cpu. if the pci bus is parked on the cpu, frame# is asserted here. (3) (3) irdy# is always asserted as frame# is deasserted. irdy# is deasserted on the clock that trdy# is sampled active. cpu_clk cpu_addr ts# aack# ta# cpu_data pci_clk pci_req# pci_gnt# pci_ad [664] pci_ad [663] c/be[3:0]# devsel# frame# irdy# trdy# 2.1.2.1 write sequence a cpu bus master begins a remote rom write transaction by initiating a one-byte, single-beat memory write transfer to cpu bus address range 4g 2m to 4g (ff80 0000h to ffff ffffh). the 660 decodes the cpu transfer, arbitrates for the pci bus, and initiates a memory write pci transaction to the same address in the 4g 2m to 4g address range. the pci agent that is controlling the remote rom (such as the pci to isa bridge), claims the transaction, manages the write cycle to the rom device, and signals trdy#.
9 an-ppc-012 the 660 then completes the pci transaction, and signals aack# and ta# to the cpu. note that remote rom writes are neither posted or pipelined. 2.1.2.2 write protection write protection can be provided by the pci agent that controls the rom. in addition, some flash rom devices can have the means to permanently lock out sectors by writing control sequences. the 660 also has a write lockout in the bridge chipset options 2 register (bit 0 of index bbh). 2.1.2.3 address, size, alignment, and endian mode in remote rom mode, cpu memory writes from 4g 2m to 4g cause the 660 to generate pci bus memory write transactions to 4g 2m to 4g. the 660 does not allow cpu masters to access the rest of the pci memory space from 2g to 4g. in remote rom mode, pci bus master memory write transactions from 4g 2m to 4g are ignored by the 660. however, the pci agent that controls the rom responds to these transactions. in contrast, in direct-attach rom mode, the 660 forwards pci bus master memory transactions from 2g to 4g (to populated memory locations) to system memory from 0 to 2g. remote rom writes must be one-byte, single-beat transfers. the endian mode of the system has no net effect on a rom write because the transfer size is one byte. the address is munged by the cpu and unmunged by the 660. the data comes out of the cpu on the byte lane associated with the munged address, and then is swapped by the 660 to the byte lane associated with the unmunged address. thus a rom write in little-endian mode puts the data byte in the same rom location as does the same rom write in big-endian mode. 2.2 rom-related bridge control registers 2.2.1 rom lockout bit for remote-attach rom the rom write-protect bit for remote rom is in the bridge chipset options 2 register (index bbh). while enabled (bit 0 is 1), writes to the remote rom are forwarded to the pci memory space. while disabled (bit 0 is 0), writes to the remote rom are treated as no-ops and an error is signalled. after the bit is set to 0 (disabled), it cannot be set to 1 (enabled).
10 an-ppc-012 ? international business machines corporation, 1996. printed in the united states of america 4/96. all rights reserved. ibm microelectronics, powerpc, powerpc 601, powerpc 603, powerpc 604, risc- watch, and aix are trademarks of the ibm corporation. ibm and the ibm logo are registered trademarks of the ibm corporation. other company names and product identifi- ers are trademarks of the respective companies. this document contains information which is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not intended for use in implantation or other direct life-support applications where malfunction may result in physical harm or injury to persons. no warranties of any kind, including but not limited to, the implied warranties of merchantability or fitness for a particular pur- pose, are offered in this document. document number: mpra12apu01 usa and canada: ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6531 tel: (800) powerpc fax: (800) powerfax http://www.chips.ibm.com http://www.ibm.com ftp://ftp.austin.ibm.com/pub/ppc_support
|
